In recent years, in flash memories as nonvolatile semiconductor memories, increased storage capacities and subdivided manufacturing processes result in decreases in the yields. In order to suppress these decreases in the yields, semiconductor memories can avoid a defect in memory cells using redundancy by replacing the faulty defective memory cells with spare memory cells are required.
Japanese Published Patent Application No.5-159597 discloses an example of these semiconductor memories. FIG. 7 is a diagram schematically illustrating a structure of this conventional semiconductor memory.
In FIG. 7, a memory cell array 101 includes memory cells (shown as MC in the figure) which are connected to (n+1) (n: positive integer) word lines WL1.about.W1n+1 and m (m: positive integer) bit lines BL1.about.BLm, and arranged like a matrix. Selection circuits Sa1.about.San in a redundancy control circuit 103 switch connections between signal lines R1.about.Rn of a row decoder 102 and the corresponding word lines WLn-WLn+1, respectively. Control cells Ca1.about.Can each have a fuse element or nonvolatile memory cell (not shown) containing defect information. output lines of the control cells Ca1.about.Can are connected to the selection circuits and their adjacent control cells, respectively.
The operation of the semiconductor memory having the above-described structure will be described. The row decoder 102 decodes an input row address, and outputs a decoded result to the signal lines R1.about.Rn. The selection circuits Sa1.about.San receive the outputs of the control cells Ca1.about.Can, and perform the switching. In this case, the i-th (1.ltoreq.i.ltoreq.n) selection circuit Sai selects the word line WLi when the output of the control cell Cai is for example "L" (Low level), and selects the word line WLi+1 when the output is "H" (High level) . The control cell Cai contains defect information of WLi. The control cell Cai outputs "H" when the defect information indicates the word line WLi has a defect or the output of Cai-1 is "H", and outputs "L" in other cases.
For example, when there is a defective memory cell MC in the i-th word line WLi, the defect information is recorded in the control cell Cai, and as for k satisfying the relationship 1.ltoreq.k&lt;i, the selection circuits Sk are controlled so as to select WLk for Rk and as for j satisfying the relationship i.ltoreq.j.ltoreq.n, the selection circuits Sj are controlled so as to select WLj+1 for Rj. That is, the redundancy control circuit 103 replaces defective memory cells with redundant memory cells by shifting the connections of the i-th and subsequent selection circuits to the word lines so as to skip the defective word line WLi as shown in FIG. 7.
The prior art semiconductor memory comprises the control cells each having the fuse element or nonvolatile memory cell containing the defect information, for all row lines. Accordingly, when the number of row lines is increased in the case of the control cells having the fuse elements, the area of the redundancy control circuit is increased and more time is required for disconnecting the fuse elements. In the case of the control cells having the nonvolatile memory cells, the area is increased due to addition of circuits for writing data, the time for recording data is increased, and further examination of memory cells which contain the defect information separately from the memory cell array is required.